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DATA SHEET
256MB Unbuffered DDR SDRAM DIMM
HB54A2568FM-A75B/B75B/10B (32M words x 64 bits, 1 Bank) HB54A2569FM-A75B/B75B/10B (32M words x 72 bits, 1 Bank)
Description
The HB54A2568FM, HB54A2569FM are Double Data Rate (DDR) SDRAM Module, mounted 256M bits DDR SDRAM (HM5425801BTT) sealed in TSOP package, and 1 piece of serial EEPROM (2k bits EEPROM) for Presence Detect (PD). The HB54A2568FM is organized as 32M x 64 x 1 bank mounted 8 pieces of 256M bits DDR SDRAM. The HB54A2569FM is organized as 32M x 72 x 1 bank mounted 9 pieces of 256M bits DDR SDRAM. Read and write operations are performed at the cross points of the CK and the /CK. This high-speed data transfer is realized by the 2 bits prefetch-pipelined architecture. Data strobe (DQS) both for read and write are available for high speed and reliable data bus design. By setting extended mode register, the on-chip Delay Locked Loop (DLL) can be set enable or disable. An outline of the products is 184-pin socket type package (dual lead out). Therefore, it makes high density mounting possible without surface mount technology. It provides common data inputs and outputs. Decoupling capacitors are mounted beside each TSOP on the module board.
Features
* 184-pin socket type package (dual lead out) Outline: 133.35mm (Length) x 31.75mm (Height) x 4.00mm (Thickness) Lead pitch: 1.27mm * 2.5V power supply (VCC/VCCQ) * SSTL-2 interface for all inputs and outputs * Clock frequency: 143MHz/133MHz/125MHz (max.) * Data inputs, outputs and DM are synchronized with DQS * 4 banks can operate simultaneously and independently (Component) * Burst read/write operation * Programmable burst length: 2, 4, 8 Burst read stop capability * Programmable burst sequence Sequential Interleave * Start addressing capability Even and Odd * Programmable /CAS latency (CL): 2, 2.5 * 8192 refresh cycles: 7.8s (8192/64ms) * 2 variations of refresh Auto refresh Self refresh
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Document No. E0088H40 (Ver. 4.0) Date Published August 2002 (K) Japan URL: http://www.elpida.com
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This product became EOL in May, 2004.
Elpida Memory, Inc. 2001-2002 Hitachi, Ltd. 2000 Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd.
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HB54A2568FM, HB54A2569FM-A75B/B75B/10B
Ordering Information
Part number HB54A2568FM-A75B*1 HB54A2568FM-B75B*2 HB54A2568FM-10B*2 HB54A2569FM-A75B*1 HB54A2569FM-B75B*2 HB54A2569FM-10B*2 Clock frequency MHz (max.) 143 MHz 133 MHz 125 MHz 143 MHz 133 MHz 125 MHz /CAS latency 2.5 2.5 2.5 2.5 2.5 2.5 Package Contact pad
184-pin dual lead out socket Gold type
Notes: 1. 133 MHz operation at /CAS latency = 2. 2. 100 MHz operation at /CAS latency = 2.
Pin Configurations
Front side 1 pin 52 pin 53 pin 92 pin
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Pin No. 1 Pin name VREF 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 DQ0 VSS DQ1 DQS0 DQ2 VCC DQ3 NC NC VSS DQ8 DQ9 DQS1 VCCQ CK1 /CK1 VSS DQ10 DQ11 CKE0 VCCQ DQ16 DQ17 DQS2 VSS
Data Sheet E0088H40 (Ver. 4.0)
93 pin Back side
144 pin 145 pin 184 pin
Pin No. 47 48
Pin name DQS8 (NC)* A0 CB2 (NC)* VSS CB3 BA1 (NC)* DQ32
1 1 1
Pin No. 93 94 95 96 97 98
Pin name VSS DQ4 DQ5 VCCQ DM0/DQS9 DQ6 DQ7 VSS NC NC NC VCCQ
Pin No. 139 140 141 142 143 144 145 146 147 148 149 150
Pin name VSS DM8/DQS17 (NC)*1 A10 CB6 (NC)*1 VCCQ CB7 (NC)*1 VSS DQ36 DQ37 VCC DM4/DQS13 DQ38 DQ39 VSS DQ44 /RAS DQ45 VCCQ /S0
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49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72
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99 VCCQ DQ33 100 101 DQS4 102 DQ34 VSS BA0 DQ35 DQ40 VCCQ /WE DQ41 /CAS VSS DQS5 DQ42 DQ43 VCC NC DQ48 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118
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DQ12 151 DQ13 152 DM1/DQS10 153 VCC 154 DQ14 155 DQ15 156 NC 157 VCCQ NC DQ20 A12 VSS DQ21 A11 158 159 160 161 162 163 164
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NC DM5/DQS14 VSS DQ46 DQ47 NC VCCQ
2
HB54A2568FM, HB54A2569FM-A75B/B75B/10B
Pin No. 27 28 29 30 31 32 33 34 35 36 37 38 39 Pin name A9 DQ18 A7 VCCQ DQ19 A5 DQ24 VSS DQ25 DQS3 A4 Pin No. 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 Pin name DQ49 VSS /CK2 CK2 VCCQ DQS6 DQ50 DQ51 VSS VCCID DQ56 DQ57 VCC DQS7 DQ58 DQ59 VSS NC SDA SCL Pin No. 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 Pin name DM2/DQS11 VCC DQ22 A8 DQ23 VSS A6 DQ28 DQ29 VCCQ DM3/DQS12 A3 DQ30 VSS DQ31 CB4 (NC)*1 CB5 (NC)* VCCQ CK0 /CK0
1
Pin No. 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184
Pin name DQ52 DQ53 NC VCC DM6/DQS15 DQ54 DQ55 VCCQ NC DQ60 DQ61 VSS DM7/DQS16 DQ62 DQ63 VCCQ SA0 SA1 SA2 VCCSPD
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VCC DQ26 40 41 42 43 44 45 46 DQ27 A2 VSS A1 CB0 (NC)*1 CB1 (NC)*1 VCC
Data Sheet E0088H40 (Ver. 4.0)
Note: 1. The HB54A2568FM assign "NC".
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HB54A2568FM, HB54A2569FM-A75B/B75B/10B
Pin Description
Pin name A0 to A12 BA0, BA1 DQ0 to DQ63 CB0 to CB7 /RAS /CAS /WE /S0 Function Address input Row address Column address Data input/output Check bit (Data input/output) Row address strobe command Column address strobe command Write enable Chip select Clock enable Clock input Differential clock input Input and output data strobe Input mask Clock input for serial PD Data input/output for serial PD Serial address input Power for internal circuit Power for DQ circuit Power for serial EEPROM Input reference voltage A0 to A12 A0 to A9
Bank select address
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CKE0 CK0 to CK2 /CK0 to /CK2 DQS0 to DQS8 SCL SDA SA0 to SA2 VCC VCCQ VCCSPD VREF VSS VCCID NC
DM0 to DM8/DQS9 to DQS17
Data Sheet E0088H40 (Ver. 4.0)
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Ground VCC identification flag No connection
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HB54A2568FM, HB54A2569FM-A75B/B75B/10B
Serial PD Matrix*
Byte No. 0 1 2 3 4 5 6
1
Function described Number of bytes utilized by module manufacturer Total number of bytes in serial PD device Memory type Number of row address Number of column address Number of DIMM banks Module data width HB54A2568FM HB54A2569FM Module data width continuation
Bit7 1 0 0 0 0 0 0 0 0
Bit6 0 0 0 0 0 0 1 1 0 0 1 1 0 1 0 0 0 0 0
Bit5 Bit4 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 0 0 0 0
Bit3 0 1 0 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0 1
Bit2 0 0 1 1 0 0 0 0 0 1 0 1 0 1 0 0 0 0 0 0 0 0 1 1
Bit1 Bit0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 0 0 0 1 1 0 1 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 1 0 0
Hex value 80 08 07 0D 0A 01 40 48 00 04 70 75 80 75 80 00 02 82 08 00 08 01 0E 04
Comments 128 256 byte SDRAM DDR 13 10 1 64 bits 72 bits 0 (+) SSTL 2.5V CL = 2.5*5
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7 8 9 -B75B -10B 10 -10B 11 12 13 14 15 16 17 18 19 20 21 22 23 -B75B/10B 24 -10B
Voltage interface level of this assembly 0 0 0 1 0 1 0 0 1 0
DDR SDRAM cycle time, CL = X -A75B
SDRAM access from clock (tAC) -A75B/B75B DIMM configuration type HB54A2568FM HB54A2569FM
0.75ns*5 0.8ns*5 None ECC 7.8 s Self refresh x8 None x8 1 CLK 2, 4, 8 4 2, 2.5 0 1
Refresh rate/type Primary SDRAM width
Error checking SDRAM width HB54A2568FM HB54A2569FM
SDRAM device attributes: Minimum clock delay back-to-back column access SDRAM device attributes: Burst length supported SDRAM device attributes: Number of banks on SDRAM device SDRAM device attributes: /CAS latency SDRAM device attributes: /CS latency SDRAM device attributes: /WE latency SDRAM module attributes SDRAM device attributes: General Minimum clock cycle time at CLX - 0.5 -A75B
Maximum data access time (tAC) from clock at CLX - 0.5 0 -A75B/B75B 1
Data Sheet E0088H40 (Ver. 4.0)
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0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 0 0 0 0 1 0 0 0 1 0 0 1 0 1 1 1 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0
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1 0 0 0 0 0 0 1 0 1 0 0 1 1 0 0 0 0 0 0 1 0 0 0 1 0 0
0C 01 02
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20 Unbuffered 0.2V C0 75 CL = 2*5 A0 75 0.75ns*5 0.8ns*5 80
5
HB54A2568FM, HB54A2569FM-A75B/B75B/10B
Byte No. 25 26 27 28 29 30 Function described Bit7 Bit6 0 0 1 0 1 0 0 1 0 0 0 0 1 1 1 1 Bit5 Bit4 0 0 0 1 0 1 1 0 0 1 0 1 0 1 0 1 0 0 1 1 1 0 1 0 1 1 1 1 1 0 1 0 Bit3 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 Bit2 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 Bit1 Bit0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 Hex value 00 00 50 3C 50 2D 32 40 90 B0 90 B0 50 60 50 60 00 41 46 4B 50 30 20ns 15ns 20ns 45ns 50ns 1 bank 256MB 0.9ns*5 1.1ns*5 0.9ns*5 1.1ns*5 0.5ns*5 0.6ns*5 0.5ns*5 0.6ns*5 Future use 65ns*5 70ns*5 75ns*5 80ns*5 12ns*5 500ps*5 600ps*5 750ps*5 1000ps*5 Comments
Minimum clock cycle time at 0 CLX - 1 Maximum data access time (tAC) from 0 clock at CLX - 1 Minimum row precharge time (tRP) Minimum row active to row active delay (tRRD) Minimum /RAS to /CAS delay (tRCD) Minimum active to precharge time (tRAS) -A75B/B75B -10B 0 0 0 0 0 0 1 1
31
Module bank density Address and command setup time before clock (tIS) -A75B/B75B -10B
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32 33 -10B 34 -10B 35 -10B 36 to 40 41 -10B 42 -10B 43 44 -10B 45 -10B 46 to 61 62 SPD revision
Address and command hold time after clock (tIH) 1 -A75B/B75B 1 0 0 0 0 Data input setup time before clock (tDS) -A75B/B75B
Data input hold time after clock (tDH) -A75B/B75B Superset information
Active command period (tRC) -A75B/B75B
Auto refresh to active/ Auto refresh command cycle (tRFC) -A75B/B75B SDRAM tCK cycle max. (tCK max.) Dout to DQS skew -A75B/B75B Data hold skew (tQHS) -A75B/B75B Superset information
Data Sheet E0088H40 (Ver. 4.0)
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0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 1 0 0 0 0 0 1 0 0 1 0 0 0 1 0 0 0 0 1 0 1 1 0 1 1 0 1 1 1 1 1 0 1 0 0 0 0 0 0 0 0
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0 0 0 0 1 0 1 0 0 1 0 1 0 0 0 0 0 0 0 0 0
32 3C
75 A0 00
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Future use 00 Initial
6
HB54A2568FM, HB54A2569FM-A75B/B75B/10B
Byte No. 63
Function described Checksum for bytes 0 to 62 HB54A2568FM-A75B HB54A2568FM-B75B HB54A2568FM-10B HB54A2569FM-A75B HB54A2569FM-B75B HB54A2569FM-10B
Bit7 1 1 1 1 1 1 0 0 x 0 0 0 0 0 0 0 0 0 0 0 0
Bit6 0 1 0 1 1 0 0 0 x 1 1 0 0 1 0 0 0 0 0 1 1
Bit5 Bit4 1 1 1 0 1 1 0 0 x 0 0 1 1 0 1 1 1 1 1 0 0 1 0 0 0 1 1 0 0 x 0 0 1 1 0 1 1 1 1 1 0 0
Bit3 0 0 0 0 0 1 0 0 x 1 0 0 0 0 0 0 0 1 1 0 1
Bit2 0 0 1 1 1 0 1 0 x 0 0 1 1 0 0 1 1 0 0 1 1 1 0 0 0 1
Bit1 Bit0 1 1 1 0 0 0 1 0 x 0 1 0 0 0 1 0 1 0 0 1 0 0 0 1 0 1 0 0 1 0 0 1 1 0 x 0 0 1 0 1 0 1 0 0 1 0 1 1 1 0 1 1
Hex value B2 E2 A7 C4 F4 B9 07 00 xx 48 42 35 34 41 32 35 36 38 39 46 4D 2D 41 42 31 37 30
Comments 178 226 167 196 244 185 HITACHI *2 (ASCII-8bit code) H B 5 4 A 2 5 6 8 9 F M -- A B 1 7 0 5 B B (Space)
64 65 to 71 72 73
Manufacturer's JEDEC ID code Manufacturer's JEDEC ID code Manufacturing location
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74 75 76 77 78 79 80 81 82 83 84 85 -B75B -10B 86 -10B 87 -10B 88 -10B 89 to 90 91 92 93 94 95 to 98 99 to 127 Revision code Revision code
Module part number Module part number Module part number Module part number Module part number Module part number Module part number Module part number Module part number HB54A2568FM HB54A2569FM
Module part number Module part number Module part number Module part number -A75B
Module part number -A75B/B75B Module part number -A75B/B75B Module part number -A75B/B75B Module part number
Manufacturing date Manufacturing date Module serial number Manufacturer specific data
Data Sheet E0088H40 (Ver. 4.0)
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0 0 1 0 1 0 1 0 0 0 0 1 0 0 0 0 0 1 1 0 0 0 1 1 0 0 0 0 0 0 0 0 0 x x *3 *4 0 0 1 1 0 0 0 0 x x 1 1 0 1 1 0 0 0 0 0 0 0 1 0 0 1 1 1 x x 0 1 0 x x 0 0 0 x x
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0 0 0 1 0 1 0 1 0 0 1 0 0 0 0 0 0 0 x x 0 0 0 0 0 0 x x x x
35 42
42 20
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20 (Space) Initial 30 20 xx xx (Space) Year code (BCD) Week code (BCD)
7
HB54A2568FM, HB54A2569FM-A75B/B75B/10B
Notes: 1. All serial PD data are not protected. 0: Serial data, "driven Low", 1: Serial data, "driven High" These SPD are based on JEDEC Committee Ballot JC-42.5-99-129. 2. Byte72 is manufacturing location code. (ex: In case of Japan, byte72 is 4AH. 4AH shows "J" on ASCII code.) 3. Bytes 95 through 98 are assembly serial number. 4. All bits of 99 through 127 are not defined ("1" or "0"). 5. These specifications are defined based on component specification, not module.
Block Diagram (HB54A2568FM)
/S0 RS DQS0 8 DQ0 to DQ7 RS RS DQS1 8 DQ8 to DQ15 RS DQS2 8 DQ16 to DQ23 RS DQS3 8 DQ24 to DQ31 DQS4 RS RS 8 RS RS 8 RS RS RS RS RS DQS DQ /CS DM RS DQS DQ /CS DM RS DM5/DQS14 DQS DQ /CS DM RS DM4/DQS13 RS DQS DQ /CS DM RS DM3/DQS12 RS DQS DQ /CS DM RS DM2/DQS11 DQS DQ /CS DM RS DM1/DQS10 RS DM0/DQS9
D0
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Data Sheet E0088H40 (Ver. 4.0)
D1
D2
D3
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DQ32 to DQ39 DQS5 DQ40 to DQ47 DQS6 DQ48 to DQ55 DQS7 DQ56 to DQ63 * D0 to D7: HM5425801 U0: 2k bits EEPROM RS: 22 VCC, VCCQ VREF VSS VCCID open Clock wiring Clock input CK0/ /CK0 CK1/ /CK1 CK2/ /CK2
D4
Note: Wire per Clock loading table/Wiring diagrams.
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D5
8 DQS DQ /CS DM
DM6/DQS15
D6
RS
DM7/DQS16
8
DQS DQ
/CS
DM
D7
D0 to D7 D0 to D7 D0 to D7
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A0 to A12 BA0, BA1 /RAS /CAS /WE CKE0 Serial PD SCL SCL SDA
A0 to A12 (D0 to D7) BA0, BA1 (D0 to D7) /RAS (D0 to D7) /CAS (D0 to D7) /WE (D0 to D7) CKE (D0 to D7)
U0
DDR SDRAMS 2DRAM loads 3DRAM loads 3DRAM loads A0 A1
SA0 SA1 SA2 Notes: 1. The SDA pull-up resistor is required due to the open-drain/open-collector output. 2. The SCL pull-up resistor is recommended because of the normal SCL line inacitve "high" state.
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SDA A2
8
HB54A2568FM, HB54A2569FM-A75B/B75B/10B
Block Diagram (HB54A2569FM)
/S0 RS DQS0 8 DQ0 to DQ7 RS DQS1 8 DQ8 to DQ15 RS DQS2 8 DQ16 to DQ23 RS DQS3 8 DQ24 to DQ31 RS DQS4 8 DQ32 to DQ39 RS DQS5 8 DQ40 to DQ47 RS DQS6 8 RS RS 8 RS RS DQS8 8 RS DQS DQ /CS DM DQS DQ /CS DM RS DM8/DQS17 DQS DQ /CS DM RS DM7/DQS16 DQ48 to DQ55 DQS7 RS DQS DQ /CS DM RS DM6/DQS15 RS DQS DQ /CS DM RS DM5/DQS14 RS DQS DQ /CS DM RS DM4/DQS13 RS DQS DQ /CS DM RS DM3/DQS12 RS DQS DQ /CS DM RS DM2/DQS11 RS DQS DQ /CS DM RS DM1/DQS10 RS DM0/DQS9
D0
D1
D2
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Data Sheet E0088H40 (Ver. 4.0)
D3
D4
D5
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DQ56 to DQ63 CB0 to CB7 * D0 to D8: HM5425801 U0: 2k bits EEPROM RS: 22 VCC, VCCQ VREF VSS VCCID open Clock wiring Clock input CK0/ /CK0 CK1/ /CK1 CK2/ /CK2
D6
D7
Note: Wire per Clock loading table/Wiring diagrams.
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D8
A0 to A12 BA0, BA1 /RAS /CAS /WE D0 to D8 D0 to D8 D0 to D8 CKE0 SCL DDR SDRAMS 3DRAM loads 3DRAM loads 3DRAM loads
A0 to A12 (D0 to D8) BA0, BA1 (D0 to D8) /RAS (D0 to D8) /CAS (D0 to D8) /WE (D0 to D8) CKE (D0 to D8)
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Serial PD SCL SDA
SDA
U0
A1
A0
A2
SA0 SA1 SA2 Notes: 1. The SDA pull-up resistor is required due to the open-drain/open-collector output. 2. The SCL pull-up resistor is recommended because of the normal SCL line inacitve "high" state.
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9
HB54A2568FM, HB54A2569FM-A75B/B75B/10B
Logical Clock Net Structure
6DRAM loads DRAM1 5DRAM loads DRAM1
CK DIMM connector
R = 120
DRAM2 DRAM3 DIMM connector DRAM4
R = 120
DRAM2 DRAM3
Capacitance DRAM5
/CK DRAM5
DRAM6
DRAM6 3DRAM loads DRAM1
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4DRAM loads R = 120 DIMM connector
DRAM1
DRAM2 Capacitance DIMM connector Capacitance DRAM5
R = 120
Capacitance DRAM3
Capacitance DRAM5
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R = 120
DRAM6 1DRAM loads
Capacitance
2DRAM loads
DRAM1
Capacitance
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Capacitance Capacitance DIMM connector Capacitance DRAM5 Capacitance
R = 120
Capacitance DRAM3
DIMM connector
Capacitance
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10
Capacitance
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Data Sheet E0088H40 (Ver. 4.0)
HB54A2568FM, HB54A2569FM-A75B/B75B/10B
Pin Functions (1)
CK (CLK), /CK (/CLK) (input pin): The CK and the /CK are the master clock inputs. All inputs except DMs, DQSs and DQs are referred to the cross point of the CK rising edge and the VREF level. When a read operation, DQSs and DQs are referred to the cross point of the CK and the /CK. When a write operation, DMs and DQs are referred to the cross point of the DQS and the VREF level. DQSs for write operation are referred to the cross point of the CK and the /CK. /S (/CS) (input pin): When /S is Low, commands and data can be input. When /S is High, all inputs are ignored. However, internal operations (bank active, burst operations, etc.) are held. /RAS, /CAS, and /WE (input pins): These pins define operating commands (read, write, etc.) depending on the combinations of their voltage levels. See "Command operation".
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Pin Functions (2)
A0 to A12 (input pins): Row address (AX0 to AX12) is determined by the A0 to the A12 level at the cross point of the CK rising edge and the VREF level in a bank active command cycle. Column address (AY0 to AY9) is loaded via the A0 to the A9 at the cross point of the CK rising edge and the VREF level in a read or a write command cycle. This column address becomes the starting address of a burst operation. A10 (AP) (input pin): A10 defines the precharge mode when a precharge command, a read command or a write command is issued. If A10 = High when a precharge command is issued, all banks are precharged. If A10 = Low when a precharge command is issued, only the bank that is selected by BA1, BA0 is precharged. If A10 = High when read or write command, auto-precharge function is enabled. While A10 = Low, auto-precharge function is disabled. BA0, BA1 (input pin): BA0/BA1 are bank select signals. The memory array is divided into bank 0, bank 1, bank 2 and bank 3. If BA1 = Low and BA0 = Low, bank 0 is selected. If BA1 = High and BA0 = Low, bank 1 is selected. If BA1 = Low and BA0 = High, bank 2 is selected. If BA1 = High and BA0 = High, bank 3 is selected. CKE (input pin): CKE controls power down and self-refresh. The power down and the self-refresh commands are entered when the CKE is driven Low and exited when it resumes to High. The CKE level must be kept for 1 CK cycle (= LCKEPW) at least, that is, if CKE changes at the cross point of the CK rising edge and the VREF level with proper setup time tIS, at the next CK rising edge CKE level must be kept with proper hold time tIH.
DQ, CB (input and output pins): Data are input to and output from these pins.
DQS (input and output pin): DQS provide the read data strobes (as output) and the write data strobes (as input). DM (input pins): DM is the reference signal of the data input mask function. DMs are sampled at the cross point of DQS and VREF VCC and VCCQ (power supply pins): 2.5V is applied. (VCC is for the internal circuit and VCCQ is for the output buffer.) VCCSPD (power supply pin): 2.5V is applied (For serial EEPROM). VSS (power supply pin): Ground is connected.
Detailed Operation Part, AC Characteristics and Timing Waveforms
Refer to the HM5425161B/HM5425801B/HM5425401B Series datasheet (E0086H10).
Data Sheet E0088H40 (Ver. 4.0)
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HB54A2568FM, HB54A2569FM-A75B/B75B/10B
Electrical Specifications
Absolute Maximum Ratings
Parameter Voltage on any pin relative to VSS Supply voltage relative to VSS Short circuit output current Power dissipation HB54A2568FM HB54A2569FM Operating temperature Storage temperature Symbol VT VCC, VCCQ IOUT PT PT Topr Tstg Value -1.0 to +4.6 -1.0 to +4.6 50 8 9 0 to +55 -50 to +100 Unit V V mA W W C C Note 1 1
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Parameter Supply voltage Input reference voltage Termination voltage DC Input high voltage DC Input low voltage DC Input signal voltage DC differential input voltage
Notes: 1. Respect to VSS. DC Operating Conditions (TA = 0 to +55C)
Symbol VCC, VCCQ VSS VREF VTT VIH VIL VIN (dc) min. 2.3 0 1.15 VREF - 0.04 VREF + 0.18 -0.3 -0.3 Typ 2.5 0 1.25 VREF -- -- -- -- max. 2.7 0 1.35 VREF + 0.04 VCCQ + 0.3 VREF - 0.18 VCCQ + 0.3 VCCQ + 0.6 Unit V V V V V V V V 1 1 1, 3 1, 4 5 6 Notes 1, 2
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VSWING (dc) 0.36
Notes: 1. 2. 3. 4. 5. 6.
All parameters are referred to VSS, when measured. VCCQ must be lower than or equal to VCC. VIH is allowed to exceed VCC up to 4.6V for the period shorter than or equal to 5ns. VIL is allowed to outreach below VSS down to -1.0V for the period shorter than or equal to 5ns. VIN (dc) specifies the allowable dc execution of each differential input. VSWING (dc) specifies the input differential voltage required for switching.
Pr
12
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Data Sheet E0088H40 (Ver. 4.0)
HB54A2568FM, HB54A2569FM-A75B/B75B/10B
DC Characteristics 1 (TA = 0 to 55C, VCC, VCCQ = 2.5V 0.2V, VSS = 0V)
x 64 Parameter Symbol Grade -A75B -B75B -10B -A75B -B75B -10B -A75B -B75B -10B -A75B -B75B -10B -A75B -B75B -10B -A75B -B75B -10B -A75B -B75B -10B -A75B -B75B -10B -A75B -B75B -10B max. 800 760 640 1240 1160 1040 144 120 96 320 280 240 200 160 120 400 360 320 1800 1720 1640 1640 1560 1480 1640 1600 1440 24 x 72 max. 900 855 720 1395 1305 1170 162 135 108 360 315 270 225 180 135 450 405 360 2025 1935 1845 1845 1755 1665 1845 1800 1620 27 Unit mA Test condition Notes
Operating current (ACTV-PRE) ICC0 Operating current (ACTVREAD-PRE) Idle power down standby current Idle standby current
CKE VIH, tRC = min. 1, 2, 5 CKE VIH, BL = 2, CL = 2.5, tRC = min. CKE VIL
ICC1
mA
1, 2, 5
ICC2P
mA
4
ICC2N
mA
CKE VIH, /CS VIH 4
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Active power down standby current Active standby current Operating current (Burst read operation) Operating current (Burst write operation) Auto refresh current Self refresh current
ICC3P
mA
CKE VIL
3
ICC3N
mA
CKE VIH, /CS VIH 3 tRAS = max. CKE VIH, BL = 2, CL = 2.5 CKE VIH, BL = 2, CL = 2.5 tRFC = min., Input VIL or VIH Input VCC - 0.2V Input 0.2V. 1, 2, 5, 6
ICC4R
mA
L
ICC4W ICC5 ICC6 Symbol ILI ILO VOH VOL
mA
1, 2, 5, 6
mA mA
Pr
min. -10 -10 max. 10 10 -- VTT - 0.76 VTT + 0.76 --
Notes. 1. 2. 3. 4. 5. 6. 7.
These ICC data are measured under condition that DQ pins are not connected. One bank operation. One bank active. All banks idle. Command/Address transition once per one cycle. Data/Data mask transition twice per one cycle. The ICC data on this table are measured with regard to tCK = min. in general.
DC Characteristics2 (TA = 0 to 55C, VCC, VCCQ = 2.5V 0.2V, VSS = 0V)
Parameter Input leakage current Output leakage current Output high voltage Output low voltage Unit A
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A V V
Test condition
Notes
VCC VIN VSS
VCC VOUT VSS
t uc
IOH (max.) = -15.2mA IOL (min.) = 15.2mA
Data Sheet E0088H40 (Ver. 4.0)
13
HB54A2568FM, HB54A2569FM-A75B/B75B/10B
Pin Capacitance (TA = 25C, VCC, VCCQ = 2.5V 0.2V) [HB54A2568FM]
Parameter Input capacitance Input capacitance Input capacitance Data and DQS input/output capacitance Symbol CI1 CI2 CI3 CO Pins Address, Cont. CKE, /S CK, /CK DQ, DQS min. max. 85 75 65 15 pF 1, 2 Unit pF pF Notes 1 1
[HB54A2569FM]
Parameter Input capacitance Symbol CI1 CI2 CI3 CO Pins Address, Cont. CKE, /S CK, /CK DQ, DQS, CB min. max. 92 82 65 15 pF 1, 2 Unit pF pF Notes 1 1
EO
Input capacitance Input capacitance Data and DQS input/output capacitance Parameter (CL = 2.5) (CL = 2.5) (CL = 2.5) (CL = 2.5) Write recovery DM to data in latency Power down entry CKE minimum pulse width
Notes: 1. These parameters are measured on conditions: f = 100MHz, VOUT = VCCQ/2, VOUT = 0.2V. 2. Dout circuits are disabled. Timing Parameter Measured in Clock Cycle for Unbuffered DIMM
Number of clock cycle Symbol tWPD tRPD tWRD tBSTW min. 3 + BL/2 BL/2 2 + BL/2 2 3 2 2.5 2 + BL/2 max.
Write to pre-charge command delay (same bank) Read to pre-charge command delay (same bank) Write to read command delay (to input all data) Burst stop command to write command delay (CL = 2) Burst stop command to DQ High-Z (CL = 2)
Read command to write command delay (to output all data) (CL = 2) Pre-charge command to High-Z (CL = 2) Write command to data in latency
Register set command to active or register set command Self refresh exit to non-read command Self refresh exit to read command
Power down exit to command input
Data Sheet E0088H40 (Ver. 4.0)
L
Pr
tBSTW tBSTZ tBSTZ tRWD tRWD tHZP tHZP tWCD tWR tDMD tMRD tSNR tSRD tPDEN tPDEX tCKEPW
od
3 + BL/2 2 2.5 1 2 0 2 10 200 1
t uc
1 1
14
HB54A2568FM, HB54A2569FM-A75B/B75B/10B
Physical Outline
Unit: mm 133.35 0.15 128.95 4.00 max (64.48) (DATUM -A-)
2.30
Component area (Front)
1 B 64.77 49.53 A 92
1.27 0.10
2 - 2.50 0.10
93
10.00
184
4.00 min
3.00 min (DATUM -A-) 6.62 2.175 R 0.90 6.35 1.80 0.10
4.00 0.10
2.50 0.20
0.20 0.15
1.00 0.05
3.80
EO
R 2.00
Component area (Back)
Detail A
Detail B
1.27 typ
Note: Tolerance on all dimensions 0.13 unless otherwise specified.
Data Sheet E0088H40 (Ver. 4.0)
15
31.75 0.15
17.80
L
Pr
od
ECA-TS2-0040-01
t uc
HB54A2568FM, HB54A2569FM-A75B/B75B/10B
CAUTION FOR HANDLING MEMORY MODULES
When handling or inserting memory modules, be sure not to touch any components on the modules, such as the memory ICs, chip capacitors and chip resistors. It is necessary to avoid undue mechanical stress on these components to prevent damaging them. In particular, do not push module cover or drop the modules in order to protect from mechanical defects, which would be electrical defects. When re-packing memory modules, be sure the modules are not touching each other. Modules in contact with other modules may cause excessive mechanical stress, which may damage the modules.
MDE0202
NOTES FOR CMOS DEVICES
EO
1 2 3
PRECAUTION AGAINST ESD FOR MOS DEVICES
Exposing the MOS devices to a strong electric field can cause destruction of the gate oxide and ultimately degrade the MOS devices operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it, when once it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. MOS devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. MOS devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor MOS devices on it.
HANDLING OF UNUSED INPUT PINS FOR CMOS DEVICES
No connection for CMOS devices input pins can be a cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. The unused pins must be handled in accordance with the related specifications.
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Power-on does not necessarily define initial status of MOS devices. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the MOS devices with reset function have not yet been initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. MOS devices are not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for MOS devices having reset function.
Data Sheet E0088H40 (Ver. 4.0)
L
Pr
16
od
t uc
CME0107
HB54A2568FM, HB54A2569FM-A75B/B75B/10B
The information in this document is subject to change without notice. Before using this document, confirm that this is the latest version.
No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Elpida Memory, Inc. Elpida Memory, Inc. does not assume any liability for infringement of any intellectual property rights (including but not limited to patents, copyrights, and circuit layout licenses) of Elpida Memory, Inc. or third parties by or arising from the use of the products or information listed in this document. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of Elpida Memory, Inc. or others. Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of the customer's equipment shall be done under the full responsibility of the customer. Elpida Memory, Inc. assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. [Product applications] Elpida Memory, Inc. makes every attempt to ensure that its products are of high quality and reliability. However, users are instructed to contact Elpida Memory's sales office before using the product in aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment, medical equipment for life support, or other such application in which especially high quality and reliability is demanded or where its failure or malfunction may directly threaten human life or cause risk of bodily injury. [Product usage] Design your application so that the product is used within the ranges and conditions guaranteed by Elpida Memory, Inc., including the maximum ratings, operating supply voltage range, heat radiation characteristics, installation conditions and other related characteristics. Elpida Memory, Inc. bears no responsibility for failure or damage when the product is used beyond the guaranteed ranges and conditions. Even within the guaranteed ranges and conditions, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating Elpida Memory, Inc. products does not cause bodily injury, fire or other consequential damage due to the operation of the Elpida Memory, Inc. product. [Usage environment] This product is not designed to be resistant to electromagnetic waves or radiation. This product must be used in a non-condensing environment. If you export the products or technology described in this document that are controlled by the Foreign Exchange and Foreign Trade Law of Japan, you must follow the necessary procedures in accordance with the relevant laws and regulations of Japan. Also, if you export products/technology controlled by U.S. export control regulations, or another country's export control laws or regulations, you must follow the necessary procedures in accordance with such laws or regulations. If these products/technology are sold, leased, or transferred to a third party, or a third party is granted license to use these products, that third party must be made aware that they are responsible for compliance with the relevant laws and regulations.
EO
Data Sheet E0088H40 (Ver. 4.0)
L
Pr
17
M01E0107
od t uc

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